A sudden change of the current flowing through a wire may induce abrupt voltage changes on that wire and its neighboring wires due to inductance. If these wires are part of the on-chip power-ground network, the induced voltage fluctuation is called Delta-I noise. (In mathematics, Delta represents time derivative so Delta-I refers to di/dt.) The Delta-I noise is equal to L di/dt, where L is a matrix of self- and mutual-inductances and i is a vector of currents on Power-ground wires. In circuits, the current spikes are caused by gate switching; therefore, a chip's di/dt measure can be defined as                                                                         ⅆ                i                                            ⅆ                t                                      ∼                          I              τ                                =                                          ⁢                                                    I                ⁢                                                                  ⁢                                  V                  dd                                                            τ                ⁢                                                                  ⁢                                  V                  dd                                                      =                                          P                                  τ                  ⁢                                                                          ⁢                                      V                    dd                                                              ∼                                                P                  ⁢                                                                          ⁢                                      f                    c                                                                    V                  dd                                                                    ,                            (                  Eq          .                                          ⁢          1                )            where I is the total average current flowing into the chip, P is the chip's power consumption, and τ is the typical rise-time of a gate, which multiplied by the chip operating frequency fc should normally be a constant, and Vdd is the voltage supplied to the chip.
A general IC design trend is that the chip power P continues to increase because of denser circuits and aggressively higher operating frequency fc. Also Vdd is constantly decreased to save power. Therefore, if this is the case, then the di/dt value should be constantly increasing. One % Delta-I noise measure is as follows:                                           %            ⁢                                                  ⁢            Delta                    -          I                =                                            L              ⁢                                                          ⁢                                                ⅆ                  i                                                  ⅆ                  t                                                                    V              dd                                ∼                                    L              ⁢                                                          ⁢              P              ⁢                                                          ⁢                              f                c                                                                    V                dd                            ⁢                                                          ⁢              2                                                          (                  Eq          .                                          ⁢          2                )            
Thus, the on-chip inductance is increasing with the constant shrink of wire width while the package inductance is only slightly decreasing. Moreover, with the introduction of lower resistivity metals, such as copper, to boost a chip's performance, the impact of the wires' inductive impedance may become compatible with the resistive portion if not larger. With all these trends, it is easy to see that the Delta-I noise will be very significant in the near future. Circuit designers have to verify and simulate their chips while considering the chips' Power- ground inductance, i.e. the matrix L.
However, due to the long range effect of partial inductive coupling, which decreases at logarithmic speed with spacing, the dimension of the L matrix can be huge and every off-diagonal mutual-coupling term is not small compared to diagonal partial self-inductance terms. This means that every two non-orthogonal wires of the Power-ground network couples to each other. Furthermore, simply ignoring smaller terms in L matrix may render the L matrix into a non-positive matrix, generating energy along with the circuit simulation and causing an incorrect simulation result.
Therefore, up until now, Power-ground simulation with the consideration of inductance and inductive coupling has been a big challenge. Researchers used Susceptance (the inverse of L matrix) or improved linear system solvers hoping to speed-up simulation but never succeeded in catching up with the increase of the number of Power-ground wires. Even if only the top two layer Power-ground wires are considered, the number of wire segments in parallel may easily go up to tens of thousands. For example, in a regular N-by-N P/G mesh, the dimension of L increases at N4.